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LTC2299 1 2299f input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 50 100 2299 ta02 67 73 74 71 150 200 C + input s/h analog input a analog input b clk a clk b 14-bit pipelined adc core clock/duty cycle control output drivers ? ? ? ov dd ognd mux d13a d0a ? ? ? ov dd ognd 2299 ta01 d13b d0b C + output drivers input s/h 14-bit pipelined adc core clock/duty cycle control , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features descriptio u applicatio s u typical applicatio u integrated dual 14-bit adcs sample rate: 80msps single 3v supply (2.7v to 3.4v) low power: 444mw 73db snr at 70mhz input 90db sfdr at 70mhz input 110db channel isolation at 100mhz multiplexed or separate data bus flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family 80msps: ltc2294 (12-bit), LTC2299 (14-bit) 65msps: ltc2293 (12-bit), ltc2298 (14-bit) 40msps: ltc2292 (12-bit), ltc2297 (14-bit) 25msps: ltc2291 (12-bit), ltc2296 (14-bit) 64-pin (9mm 9mm) qfn package dual 14-bit, 80msps low power 3v adc the ltc ? 2299 is a 14-bit 80msps, low power dual 3v a/d converter designed for digitizing high frequency, wide dynamic range signals. the LTC2299 is perfect for demanding imaging and communications applications with ac performance that includes 73db snr and 90db sfdr for signals well beyond the nyquist frequency. dc specs include 1.2lsb inl (typ), 0.5lsb dnl (typ) and 0.5lsb inl, 0.5lsb dnl over temperature. the transition noise is a low 1.2lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.3v logic. an optional multiplexer allows both channels to share a digital output bus. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. snr vs input frequency, ?db, 2v range wireless and wired broadband communication imaging systems spectral analysis portable instrumentation
LTC2299 2299f 2 parameter conditions min typ max units resolution (no missing codes) 14 bits integral linearity error differential analog input (note 5) C5 1.2 5 lsb differential linearity error differential analog input C1 0.5 1 lsb offset error (note 6) C12 212 mv gain error external reference C2.5 0.5 2.5 %fs offset drift 10 v/ c full-scale drift internal reference 30 ppm/ c external reference 15 ppm/ c gain matching external reference 0.3 %fs offset matching 2mv transition noise sense = 1v 1.2 lsb rms absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... C0.3v to 1v analog input voltage (note 3) ..... C0.3v to (v dd + 0.3v) digital input voltage .................... C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range LTC2299c ............................................... 0 c to 70 c LTC2299i .............................................C40 c to 85 c storage temperature range ..................C65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number qfn part* marking LTC2299up LTC2299cup LTC2299iup consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) co verter characteristics u top view 65 up package 64-lead (9mm 9mm) plastic qfn t jmax = 125 c, ja = 20 c/w exposed pad (pin 65) is gnd and must be soldered to pcb a ina + 1 a ina C 2 refha 3 refha 4 refla 5 refla 6 v dd 7 clka 8 clkb 9 v dd 10 reflb 11 reflb 12 refhb 13 refhb 14 a inb C 15 a inb + 16 48 da7 47 da6 46 da5 45 da4 44 da3 43 da2 42 da1 41 da0 40 ofb 39 db13 38 db12 37 db11 36 db10 35 db9 34 db8 33 db7 64 gnd 63 v dd 62 sensea 61 vcma 60 mode 59 shdna 58 oea 57 ofa 56 da13 55 da12 54 da11 53 da10 52 da9 51 da8 50 ognd 49 ov dd gnd 17 v dd 18 senseb 19 vcmb 20 mux 21 shdnb 22 oeb 23 db0 24 db1 25 db2 26 db3 27 db4 28 db5 29 db6 30 ognd 31 ov dd 32
LTC2299 3 2299f symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 73 db 40mhz input 70.1 73 db 70mhz input 73 db 140mhz input 72.6 db sfdr 5mhz input 90 db 40mhz input 74 90 db 70mhz input 90 db 140mhz input 85 db sfdr 5mhz input 90 db 40mhz input 80 90 db 70mhz input 90 db 140mhz input 90 db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 72.9 db 40mhz input 69.5 72.8 db 70mhz input 72.8 db 140mhz input 72.1 db i md intermodulation distortion f in = 40mhz, 90 db 41mhz crosstalk f in = 100mhz C110 db spurious free dynamic range 4th harmonic or higher spurious free dynamic range 2nd or 3rd harmonic symbol parameter conditions min typ max units v in analog input range (a in + Ca in C ) 2.7v < v dd < 3.4v (note 7) 1v to 2v v v in,cm analog input common mode differential input (note 7) 1 1.5 1.9 v i in analog input leakage current 0v < a in + , a in C < v dd C1 1 a i sense sensea, senseb input leakage 0v < sensea, senseb < 1v C3 3 a i mode mode input leakage current 0v < mode < v dd C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4)
LTC2299 2299f 4 digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 30 ppm/ c v cm line regulation 2.7v < v dd < 3.4v 3 mv/v v cm output resistance C1ma < i out < 1ma 4 ? symbol parameter conditions min typ max units logic inputs (clk, oe, shdn, mux) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10 a 2.995 v i o = C200 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = C200 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
LTC2299 5 2299f symbol parameter conditions min typ max units f s sampling frequency (note 9) 1 80 mhz t l clk low time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 9) 5 6.25 500 ns t h clk high time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 9) 5 6.25 500 ns t ap sample-and-hold aperture delay 0 ns t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns t md mux to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 7) 4.3 10 ns bus relinquish time (note 7) 3.3 8.5 ns pipeline latency 6 cycles symbol parameter conditions min typ max units v dd analog supply voltage (note 9) 2.7 3 3.4 v ov dd output supply voltage (note 9) 0.5 3 3.6 v iv dd supply current both adcs at f s(max) 148 172 ma p diss power dissipation both adcs at f s(max) 444 516 mw p shdn shutdown power (each channel) shdn = h, oe = h, no clk 2 mw p nap nap mode power (each channel) shdn = h, oe = l, no clk 15 mw power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 80mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 80mhz, input range = 1v p-p with differential drive. the supply current and power dissipation are the sum total for both channels with both channels active. note 9: recommended operating conditions.
LTC2299 2299f 6 code 0 dnl error (lsb) 0.2 0.4 0.6 16384 2299 g03 0 C0.2 C1.0 4096 8192 12288 C0.6 C0.4 C0.8 1.0 0.8 code 0 inl error (lsb) 0 0.5 1.0 16384 2299 g02 C0.5 C1.0 C2.0 4096 8192 12288 C1.5 2.0 1.5 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, ?db, 2v range typical perfor a ce characteristics uw typical inl, 2v range, 80msps typical dnl, 2v range, 80msps 8192 point fft, f in = 5mhz, ?db, 2v range, 80msps 8192 point fft, f in = 30mhz, ?db, 2v range, 80msps 8192 point fft, f in = 70mhz, ?db, 2v range, 80msps 8192 point fft, f in = 140mhz, ?db, 2v range, 80msps grounded input histogram, 80msps crosstalk vs input frequency input frequency (mhz) 0 ?30 crosstalk (db) ?25 ?20 ?15 ?10 ?05 ?00 20 40 60 80 2299 g01 100 frequency (mhz) 0 amplitude (db) C60 C40 C20 0 35 2299 g04 C80 C100 C70 C50 C30 C10 C90 C110 C120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) C60 C40 C20 0 35 2299 g05 C80 C100 C70 C50 C30 C10 C90 C110 C120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) C60 C40 C20 0 35 2299 g06 C80 C100 C70 C50 C30 C10 C90 C110 C120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) C60 C40 C20 0 35 2299 g07 C80 C100 C70 C50 C30 C10 C90 C110 C120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) C60 C40 C20 0 35 2299 g08 C80 C100 C70 C50 C30 C10 C90 C110 C120 5 15 25 10 20 30 40 code 8201 26 178 552 1987 5194 6150 35969 8203 8205 8207 8209 count 30000 40000 50000 2299 g09 20000 10000 25000 35000 45000 15000 5000 0 12558 43161 25292
LTC2299 7 2299f typical perfor a ce characteristics uw snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db snr and sfdr vs clock duty cycle, 80msps snr vs input level, f in = 70mhz, 2v range, 80msps i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v i vdd vs sample rate, 5mhz sine wave input, ?db sfdr vs input level, f in = 70mhz, 2v range, 80msps sfdr vs input frequency, ?db, 2v range, 80msps sample rate (msps) 0 95 i vdd (ma) 105 125 135 145 165 10 50 70 2299 g16 115 155 40 90 100 20 30 60 80 2v range 1v range sample rate (msps) 0 0 i ovdd (ma) 2 6 8 10 14 10 50 70 2299 g17 4 12 40 90 100 20 30 60 80 snr vs input frequency, ?db, 2v range, 80msps input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 50 100 2299 g10 67 73 74 71 150 200 input frequency (mhz) 0 85 90 100 150 2299 g11 80 75 50 100 200 70 65 95 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 80 90 100 80 2299 g12 70 60 50 10 20 30 40 50 60 70 90 100 110 sfdr snr clock duty cycle (%) 30 snr and sfdr (dbfs) 85 90 60 2299 g13 80 75 40 50 35 65 45 55 70 70 95 sfdr: dcs on snr: dcs on snr: dcs off sfdr: dcs off input level (dbfs) ?0 ?0 ?0 snr (dbc and dbfs) 30 40 50 ?0 0 2299 g14 20 10 0 ?0 ?0 dbfs dbc ?0 60 70 80 input level (dbfs) ?0 sfdr (dbc and dbfs) 60 dbc dbfs 90 100 0 2299 g15 50 40 0 ?0 ?0 ?0 20 120 110 80 70 30 10 100dbc sfdr reference line
LTC2299 2299f 8 uu u pi fu ctio s a ina + (pin 1): channel a positive differential analog input. a ina (pin 2): channel a negative differential analog input. refha (pins 3, 4): channel a high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refla (pins 5, 6): channel a low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 10, 18, 63): analog 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. clka (pin 8): channel a clock input. the input sample starts on the positive edge. clkb (pin 9): channel b clock input. the input sample starts on the positive edge. reflb (pins 11, 12): channel b low reference. short together and bypass to pins 13, 14 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 13, 14 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. refhb (pins 13, 14): channel b high reference. short together and bypass to pins 11, 12 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 11, 12 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. a inb (pin 15): channel b negative differential analog input. a inb + (pin 16): channel b positive differential analog input. gnd (pins 17, 64): adc power ground. senseb (pin 19): channel b reference programming pin. connecting senseb to v cmb selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to senseb selects an input range of v senseb . 1v is the largest valid input range. v cmb (pin 20): channel b 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cma . mux (pin 21): digital output multiplexer control. if mux is high, channel a comes out on da0-da13, ofa; channel b comes out on db0-db13, ofb. if mux is low, the output busses are swapped and channel a comes out on db0- db13, ofb; channel b comes out on da0-da13, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. shdnb (pin 22): channel b shutdown mode selection pin. connecting shdnb to gnd and oeb to gnd results in normal operation with the outputs enabled. connecting shdnb to gnd and oeb to v dd results in normal opera- tion with the outputs at high impedance. connecting shdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting shdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance. oeb (pin 23): channel b output enable pin. refer to shdnb pin function. db0 ?db13 (pins 24 to 30, 33 to 39): channel b digital outputs. db13 is the msb. ognd (pins 31, 50): output driver ground. ov dd (pins 32, 49): positive supply for the output driv- ers. bypass to ground with 0.1 f ceramic chip capacitor. ofb (pin 40): channel b overflow/underflow output. high when an overflow or underflow has occurred. da0 ?da13 (pins 41 to 48, 51 to 56): channel a digital outputs. da13 is the msb. ofa (pin 57): channel a overflow/underflow output. high when an overflow or underflow has occurred. oea (pin 58): channel a output enable pin. refer to shdna pin function.
LTC2299 9 2299f shdna (pin 59): channel a shutdown mode selection pin. connecting shdna to gnd and oea to gnd results in normal operation with the outputs enabled. connecting shdna to gnd and oea to v dd results in normal opera- tion with the outputs at high impedance. connecting shdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting shdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance. mode (pin 60): output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects straight bi- nary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle uu u pi fu ctio s stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. v cma (pin 61): channel a 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cmb . sensea (pin 62): channel a reference programming pin. connecting sensea to v cma selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sensea selects an input range of v sensea . 1v is the largest valid input range. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. fu n ctio n al block diagra uu w figure 1. functional block diagram (only one channel is shown) shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2299 f01 input s/h sense v cm a in a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d13 d0
LTC2299 2299f 10 dual digital output bus timing (only one channel is shown) ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ?5 n ?4 n ?3 n ?2 clk d0-d13, of 2299 td01 n ?6 n ?1 multiplexed digital output bus timing t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a ?6 b ?6 b ?6 a ?6 a ?5 b ?5 b ?5 a ?5 a ?4 b ?4 b ?4 a ?4 a ?3 b ?3 b ?3 a ?3 a ?2 b ?2 a + 2 a + 4 a + 3 a analog input a t h t d t md t l clka = clkb = mux d0a-d13a, ofa 2299 td02 d0b-d13b, ofb
LTC2299 11 2299f dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, applicatio s i for atio wu uu 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches midsupply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ) ? f in ? t jitter crosstalk crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a C1dbfs signal). converter operation as shown in figure 1, the LTC2299 is a dual cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value six cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive
LTC2299 2299f 12 applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the LTC2299 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the applicatio s i for atio wu u u third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the LTC2299 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capaci- tance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from figure 2. equivalent input circuit v dd v dd v dd 15 ? 15 ? c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf LTC2299 a in + a in clk 2299 f02
LTC2299 13 2299f high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the LTC2299 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample- and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may applicatio s i for atio wu uu degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the LTC2299 being driven by an rf transformer with a center tapped secondary. the second- ary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans- former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm LTC2299 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 2299 f03 figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies.
LTC2299 2299f 14 figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. applicatio s i for atio wu uu figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz figure 8. recommended front end circuit for input frequencies above 300mhz figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2299 f06 LTC2299 figure 5. single-ended drive figure 4. differential drive with an amplifier 25 ? 25 ? 12pf 2.2 f v cm 2299 f04 + + cm analog input high speed differential amplifier a in + a in LTC2299 25 ? 0.1 f analog input v cm a in + a in C 1k 12pf 2299 f05 2.2 f 1k 25 ? 0.1 f LTC2299 the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2299 f07 LTC2299 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 2299 f08 6.8nh 6.8nh LTC2299
LTC2299 15 2299f applicatio s i for atio wu uu reference operation figure 9 shows the LTC2299 reference circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. each adc channel has an independent reference with its own bypass capacitors. the two channels can be used with the same or different input ranges. other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. for the best channel matching, connect an external reference to sensea and senseb. figure 10. 1.5v range adc figure 9. equivalent reference circuit v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 2299 f09 4 ? diff amp 1 f 1 f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control LTC2299 v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 2299 f10 LTC2299 input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.7db. see the typical performance charac- teristics section. driving the clock input the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low jitter squaring circuit before the clk pin (figure 11).
LTC2299 2299f 16 applicatio s i for atio wu uu the noise performance of the LTC2299 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. it is recommended that clka and clkb are shorted together and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clka and clkb can be driven by two different signals. if this delay exceeds 1ns, the performance of the part may degrade. clka and clkb should not be driven by asynchronous signals. maximum and minimum conversion rates the maximum conversion rate for the LTC2299 is 80msps. for the adc to operate properly, the clk signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 5.9ns for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the mode pin controls both channel a and channel bthe duty cycle stabilizer is either on or off for both channels. the lower limit of the LTC2299 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the LTC2299 is 1msps. digital outputs digital output buffers figure 12 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 ? to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the LTC2299 should drive a minimal capacitive load to avoid possible interaction between the figure 11. sinusoidal single-ended clk drive clk 50 ? 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean supply sinusoidal clock input 2299 f11 nc7svu04 LTC2299
LTC2299 17 2299f digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the LTC2299 parallel digital output can be selected for offset binary or 2s complement format. note that mode controls both channel a and channel b. connecting mode to gnd or 1/3v dd selects straight binary output format. connecting mode to 2/3v dd or v dd selects 2s complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 1 shows the logic states for the mode pin. applicatio s i for atio wu u u overflow bit when of outputs a logic high the converter is either overranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. channels a and b have independent output enable pins (oea, oeb). table 1. mode pin function clock duty mode pin output format cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off figure 12. digital output buffer 2299 f12 ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to v dd predriver logic data from latch oe LTC2299
LTC2299 2299f 18 applicatio s i for atio wu u u sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent shdn pins (shdna, shdnb). channel a is controlled by shdna and oea, and channel b is controlled by shdnb and oeb. the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operat- ing while the other channel is in nap or sleep mode. digital output mulitplexer the digital outputs of the LTC2299 can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on da0-da13, ofa; channel b comes out on db0-db13, ofb. if mux is low, the output busses are swapped and channel a comes out on db0-db13, ofb; channel b comes out on da0-da13, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode). the multiplexed data is available on either data busthe un- used data bus can be disabled with its oe pin. grounding and bypassing the LTC2299 requires a printed circuit board with a clean, unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the LTC2299 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the LTC2299 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area.
LTC2299 19 2299f applicatio s i for atio wu u u c21 0.1 f c27 0.1 f v dd v dd v dd v dd v dd v cc v cmb c20 2.2 f c18 1 f c23 1 f c34 0.1 f c31 * c17 0.1 f c14 0.1 f c25 0.1 f c28 2.2 f c35 0.1 f c24 0.1 f c36 4.7 f e3 v dd 3v e5 pwr gnd v dd v cc 2299 ai01 c1 0.1 f r16 33 ? r32 opt r39 opt r1 1k r2 1k r3 1k r10 1k r14 49.9 ? r20 24.9 ? r18 * r24 * r17 opt r22 24.9 ? r23 51 t2 * c29 0.1 f c33 0.1 f j3 clock input u6 nc7svu04 u3 nc7svu04 24 3 5 u4 nc7sv86p5x c22 0.1 f c15 0.1 f c12 4.7 f 6.3v l1 bead v dd c19 0.1 f c11 0.1 f c4 0.1 f c2 2.2 f c10 2.2 f c9 1 f c13 1 f r15 1k j4 analog input b v cc 1 2 3 4 ?? 5 v cmb c8 0.1 f c6 * c44 0.1 f r6 24.9 ? r5 * r9 * r4 opt r7 24.9 ? r8 51 t1 * c3 0.1 f c7 0.1 f j2 analog input a 1 2 3 5 ?? 4 v cma v cma 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp1 mode r34 4.7k r n1a 33 ? r n1b 33 ? r n1c 33 ? r n1d 33 ? r n2a 33 ? r n2b 33 ? r n2c 33 ? r n2d 33 ? r n3a 33 ? r n3b 33 ? r n3c 33 ? r n3d 33 ? r n4a 33 ? r n4b 33 ? r n4c 33 ? r n5a 33 ? r n5b 33 ? r n5c 33 ? r n5d 33 ? r n6a 33 ? r n6b 33 ? r n6c 33 ? r n6d 33 ? c39 1 f c38 0.01 f v cc v dd byp gnd adj out shdn gnd in 1 2 3 4 8 u8 lt1763 7 6 5 gnd r26 100k r25 105k c37 10 f 6.3v c46 0.1 f e4 gnd c45 100 f 6.3v opt c40 0.1 f c48 0.1 f c47 0.1 f a ina + a ina C refha refha refla refla v dd clka clkb v dd reflb reflb refhb refhb a inb C a inb + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 da7 da6 da5 da4 da3 da2 da1 da0 ofb db13 db12 db11 db10 db9 db8 db7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd v dd sensea vcma mode shdna oea ofa da13 da12 da11 da10 da9 da8 ognd ov dd gnd v dd senseb vcmb mux shdnb oeb db0 db1 db2 db3 db4 db5 db6 ognd ov dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e2 ext ref b 12 v dd 34 v cm v dd v cmb 56 ext ref jp3 sense e1 ext ref a 12 v dd 34 v cm v dd 56 ext ref jp2 sensea c5 0.1 f v cc b4 b5 b3 b2 b1 b0 oe b6 b7 a4 a6 a7 11 12 13 14 15 16 17 18 19 9 20 v cc 74vcx245bqx v cc 8 7 6 5 4 3 2 1 10 a5 a0 t/r gnd a2 a3 a1 b4 b5 b3 b2 b1 b0 oe b6 b7 a4 a6 a7 11 12 13 14 15 16 17 18 19 9 20 v cc 74vcx245bqx v cc 8 7 6 5 4 3 2 1 10 a5 a0 t/r gnd a2 a3 a1 u5 24lc025 a0 a1 a2 a3 v cc wp scl sda 1 2 3 4 8 7 6 5 24 3 5 u2 u9 b4 b5 b3 b2 b1 b0 oe b6 b7 a4 a6 a7 11 12 13 14 15 16 17 18 19 9 20 v cc 74vcx245bqx v cc 8 7 6 5 4 3 2 1 10 a5 a0 t/r gnd a2 a3 a1 b4 b5 b3 b2 b1 b0 oe b6 b7 a4 a6 a7 11 12 13 14 15 16 17 18 19 9 20 v cc 74vcx245bqx v cc 8 7 6 5 4 3 2 1 10 a5 a0 t/r gnd a2 a3 a1 u10 u11 r n7a 33 ? r n7b 33 ? r n7c 33 ? r n7d 33 ? r n8a 33 ? r n8b 33 ? 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 80 82 84 86 88 90 92 94 96 98 100 79 81 83 85 87 89 91 93 95 97 99 v cc v ss scl sda r33 4.7k enable v ccin j1 edge-con-100 r35 100k 1 4 5 3 2 + c41 0.1 f r38 4.99k r37 4.99k r36 4.99k scl v ccin v ss sda assembly type dc851a-a dc851a-f u1 LTC2299iup LTC2299iup r5, r9, r18, r24 24.9 ? 12.4 ? c6, c31 12pf 8pf t1, t2 etc1-1t etc1-1-13 input frequency f in < 70mhz f in > 70mhz *version table u1 LTC2299
LTC2299 2299f 20 applicatio s i for atio wu u u silkscreen top top side
LTC2299 21 2299f applicatio s i for atio wu u u inner layer 2 gnd inner layer 3 power
LTC2299 2299f 22 applicatio s i for atio wu u u bottom side
LTC2299 23 2299f package descriptio u up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom view?xposed pad 7.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (up64) qfn 1003 recommended solder pad pitch and dimensions 0.70 0.05 7.15 0.05 (4 sides) 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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